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Target Configuration Space
Table 7-7 · Status Register 06 Hex
Bit(s)
2:0
3
4
5
6
7
8
10:9
11
12
13
14
15
Bit(s)
0
2:1
3
31:4
Type
RO
RO
RO
RO
RO
RO
RW
RO
RW
RW
RW
RW
RW
Type
RO
RO
RO
RW/RO
Description
Reserved. Set to '000'.
Interrupt Status
This bit reflects the status of the INTAn output.
Capabilities List
This is set to 1. CorePCIF implements a vendor capability ID and optional hot-swap capability.
66 MHz Capable
Set to 1 to indicate a 66 MHz Target, or 0 to indicate a 33 MHz Target. The value is set by the MHZ_66
parameter.
UDF Supported
Set to 0 (no user definable features).
Fast Back-to-Back Capable
Set to 0 (fast back-to-back to same agent only).
Data Parity Error Detected
If the Master controller detects a PERRn, this bit is set to 1. This bit is read-only in Target-only implementations
and is set to 0. It is cleared by writing a '1'.
DEVSELn timing
Set to '10' (slow DEVSELn response).
Signaled Target Abort
Set to 0 at system reset. This bit is set to 1 by internal logic whenever a Target abort cycle is executed. It is cleared by
writing a '1'.
Received Target Abort
If the Master controller detects a Target Abort, this bit is set to 1. This bit is read-only in Target-only
implementations and is set to 0. It is cleared by writing a '1'.
Received Master Abort
If the Master controller performs a Master Abort, this bit is set to 1. This bit is read-only in Target-only
implementations and is set to 0. It is cleared by writing a '1'.
Signaled System Error
Set to 0 at system reset. This bit is set to 1 by internal logic whenever the Target asserts the SERRn signal. It is
cleared by writing a '1'.
Detected Parity Error
Set to 0 at system reset. This bit is set to 1 by internal logic whenever a parity error, address, or data is detected,
regardless of the value of bit 6 in the command register. It is cleared by writing a '1'.
Table 7-8 · Base Address Registers (memory) 10 Hex to 24 Hex
Description
Memory Space Indicator. Set to 0.
Set to '00' to indicate anywhere in 32-bit address space.
Prefetchable. Set by the BAR i _PREFETCH parameter.
Base Address. Depending on the BAR i _ADDR_WIDTH parameter, these bits may be writable or read-only. If a
128 kB address space is set (BAR i _ADDR_WIDTH = 17), bits 31:17 will be readable/writable, and bits 16:4 will
be read-only and set to 0.
v4.0
109
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